От: fpga journal update [news@fpgajournal.com]
Отправлено: 16 марта 2004 г. 22:48
Кому: Michael Dolinsky
Тема: FPGA Journal Update Vol II No 11


a techfocus media publication :: March 16, 2004 :: volume II, no. 11


FROM THE EDITOR

This week we have one of the most significant announcements to come down the pike in recent times in the FPGA tools space. Synopsys is re-entering the FPGA synthesis market with their newly announced Design Compiler FPGA. Synopsys' press release has the details and our first feature article "A Sleeping Giant Awakes" speculates about the impact on the industry.

Our second feature this week "Raising the Bar" takes a look at the innovative design techniques used by Nallatech, Ltd. of Scotland in developing a high-performance image processing system. Nallatech's design expertise and creativity in setting up their design flow gave them a cutting-edge answer to a complex design problem in near-record time.

Finally, we take a look at the continuing controversy over market share numbers, and offer our musings on their recency, reliability, and relevance in our "Tilting at Tech Market Windmills."

Thanks for reading!

If there's anything we can do to make our publications more useful to you, please let us know at: comments@fpgajournal.com

Kevin Morris – Editor
FPGA and Programmable Logic Journal

LATEST NEWS

Tuesday, March 16, 2004

Lattice Releases IP Core for Serial RapidIO® Applications

Xilinx Japan Announces Distributor Agreement with Ryoyo Electro Corporation

AccelChip Joins Synopsys in-Sync Program; Company to Offer Immediate Support of Design Compiler, Design Compiler FPGA Flows

Monday, March 15, 2004

Synopsys Delivers New FPGA Synthesis Solution to Solve the Toughest Prototyping Challenges

Texas Instruments Veteran Kevin McGarity Joins Altera Board

Altera Announces Stratix GX Design-in Kit for Cadence Allegro Platform

ISSI Introduces an Innovative Alternative to CAMs

Altium to Host LiveEvent at electronicaUSA/Embedded Systems Conference 2004

Aldec's HDL Simulator Supports Altera's Stratix II Device Family

Thursday, March 11, 2004

Xilinx Announces Proven Interoperability Between Xilinx Virtex-II Pro FPGAs and Intel IXP2800 Network Processor

Si2 Announces the Third Annual OpenAccess Conference To Feature Speakers and Demonstrations From Leading Semiconductor and EDA Companies; Number of Papers Triples since Last Conference

AccelChip Expands into Japan and Korea with K.K. Rocky

Wednesday, March 10, 2004

Altera CEO John Daane to Discuss ASIC and FPGA Design Flow Synergy at SNUG 2004

Insight Memec Develops the First Xilinx Virtex-II Pro LC Development Kit Priced Under $200

Cypress Delivers Design Kit for Industry's Highest-Performance Network Search Engines


ANNOUNCEMENTS

World's Lowest Power FPGAs: With standby current as low as 22uA, QuickLogic's Eclipse II FPGA family helps designers meet stringent power budgets. In battery powered and handheld systems, using QuickLogic's FPGAs extends battery life by helping minimize power consumption. In AC-powered systems, the power decrease can reduce the cost and noise of cooling systems, while increasing system reliability.
Click here for more information.


Learn a Bunch, Save a Bundle with Insight Memec/Xilinx Workshops

Spartan™-3 Workshop
Learn Spartan-3 FPGAs and ISE design tools. Get the Spartan-3 LC development kit for under $200 (USD).
http://www.insight.na.memec.com/s3_workshop
Or call 800.677.7716

UltraController™ Workshop
Learn Virtex-II Pro™ FPGAs and the UltraController solution. Get the Virtex-II Pro LC development kit for under $200 (USD).
http://www.insight.na.memec.com/uc_workshop
Or call 800.677.7716

*Attend a workshop free when you order either kit from Insight Memec.



Visit Techfocus Media

CURRENT FEATURE ARTICLES

A Sleeping Giant Awakes
Synopsys enters FPGA - for real
Raising the Bar
Nallatech elevates FPGA-based system design
Tilting at Tech Market Windmills
The debate over Dataquest numbers
Aftermarket Avalanche
New Products Propel FPGAs into a Broader Base
A Wolf in Sheep's Clothing
Altera introduces MAX II
Top-Down DSP Design Flow to Silicon Implementation
by Dan Ganousis, AccelChip, Inc.
Physics Drives Physical into the Mainstream
New demands on design tools
Accelerating VoIP
A. Tavoularis, M.G. Manousos, D. Economou,
G. Lykakis (National Technical University of Athens)

All is Not SRAM
A survey of flash, antifuse, and EE programmable logic

A Sleeping Giant Awakes
Synopsys enters FPGA - for real

Synopsys is no stranger to the FPGA market. They have made several fateful forays onto the playing field of programmable logic in the past. Like Salvador Dali’s “Gala Contemplating the Mediterranean Sea Which at Twenty Meters Becomes the Portrait of Abraham Lincoln,” the true nature of Synopsys’ FPGA strategy was best observed from a distance. From up-close, it appeared that they were putting meager development effort into a mediocre product that was nearly given away in the EDA industry’s closest thing to a commodity tools market. From far away, however, maybe even with your eyes blurred a bit, another explanation emerged. It is possible that the company, whose lifeblood was a 9-digit annual income from ASIC synthesis, was entering the FPGA market as a defensive strategy. By offering adequate tools for a pittance, they helped discourage the fledgling FPGA synthesis suppliers from gaining the monetary momentum that would allow an upstart competitor to develop synthesis technology that could compete with their flagship Design Compiler.

That was then, and this is now. The new reality has three important differences from the days when Synopsys last actively played in FPGA. First is the fact that the high-end ASIC synthesis market is now driven by risk aversion rather than technology leadership. Most design team managers who value their jobs are not going to gamble an NRE on any tool other than the one that has proven itself on thousands of ASIC designs, regardless of the possible features, benefits, and productivity gains offered by a competitive tool. Second, although Synopsys’ strategy may have postponed the inevitable, a competitor, Synplicity, has managed to develop synthesis technology that rivals theirs. Third, with design starts migrating to FPGA from every direction – ASIC, DSP, SoC, and ASSP, it is impossible to maintain a belief that an ASIC-centric market will continue to account for the majority of EDA revenue. In the same painful way that the FPGA market had to come to grips with the necessary diversification beyond telecom, the EDA market must now accept that building more and more expensive and complex tools for a smaller and smaller ASIC design community is not the path to growth. [more]

Raising the Bar
Nallatech elevates FPGA-based system design

It’s fun sometimes to see how the pros do things. I find it inspiring (and a little bit humbling) to watch someone who’s good enough at what they do to throw the book away and use their intimate, almost intuitive understanding of the subject to accomplish great things with an elegance of simplicity that belies the difficulty of the task.

Nallatech, LTD. of Scotland is well known as one of the leading experts in Xilinx FPGAs. They provide a wide range of high-performance computing products on FPGA-based platforms as well as developing custom solutions for specific clients. In interviewing them about one of their recent projects, I immediately got the sensation of watching masters at work.

Their challenge was to design a complex multi-board image processing system with a mass storage interface. They had to complete the design in only 4 months combining digital signal processing (DSP), high-speed serial interfaces, and multiple system-on-chip designs with parallel processors and custom hardware and software components. What they brought to the party was a highly experienced team, previous designs from which they could borrow technology, and an established design process with the flexibility to incorporate innovation. [more]

Tilting at Tech Market Windmills
The debate over Dataquest numbers

In John Cooley’s column last week, he raised long overdue questions on the myth of market share perpetuated by Dataquest’s annual pilgrimage down the mountain with their stone scoreboards showing who supposedly won the year-before-last championship in the FPGA synthesis market. Perhaps we should suppress our collective yawns long enough to take a look at the relevance and reliability of the metrics provided by these market-share mavens.

Every year about this time, Dataquest sends out their analysis of various technology markets. Among those is a measure of the relative market share of EDA tools in various categories such as FPGA synthesis. The report unceremoniously declares the size of the market segment and the product revenue claimed by each competitor. Then, through the miracle of Microsoft Excel, it provides the percent of market share for each. The business model for this is curious and clever. The research firm essentially collects data from each company, then sells the same data back to them a year later after summarizing, sanitizing, and cross-checking it. [more]


You're receiving this newsletter because you subscribed at our website www.fpgajournal.com.
If someone forwarded this newsletter to you and you'd like to receive your own free subscription, go to: www.fpgajournal.com/update.
If at any time, you would like to unsubscribe, send e-mail to unsubscribe@fpgajournal.com. (But we hope you don't.)
If you have any questions or comments, send them to comments@fpgajournal.com.

All material copyright © 2003-2004 techfocus media, inc. All rights reserved.
Privacy Statement